| 摘要 |
<p>A multiprocessor computer system having a first processor having a first interrupt mechanism for generating interrupt requests, a second processor having a second interrupt mechanism, and a system bus for communicating interrupt requests from the first processor to the second processor. The second interrupt mechanism is responsive to an interrupt request by generating an acknowledge response on the system bus when the second processor accepts the interrupt request and generating a not acknowledge response on the system bus when the second processor contains a previous and pending interrupt request of higher level and refuses the interrupt request. The second interrupt mechanism is responsive to the completion of servicing of an interrupt request by the second processor by placing on the system bus an interrupt completed command, which includes an address identifying the second processor and a code indicating that the second processor has completing servicing an interrupt request. The first processor includes an interrupt retry means, which includes a refused interrupt register means responsive to a not acknowledge response from the second processor in response to an interrupt requested from the first processor for storing the channel number of the second processor, and level monitor logic connected from the system bus. The level monitor logic detects the occurrence of an interrupt completed command on the system bus, compares the address in the interrupt completed command to a second processor identification stored in the refused interrupt register means, and generates a retry interrupt output to the first processor when the address in the interrupt completed command corresponds to a second processor identification stored in the refused interrupt register means. The first processor is responsive to an interrupt retry output from the level monitor means by retrying the corresponding previously refused interrupt request. <IMAGE></p> |
