| 摘要 |
A write protection apparatus is disclosed. The write protection apparatus couples a data supplying device (121) to the data input of a memory device (127). The memory protection device generates a first signal (211) which triggers generation of a second signal (215). The second signal (215) is active for a first predetermined time and is coupled to the input of the memory device (127). At any time during this first predetermined time, a third signal (209) may be generated. The third signal (209) inactivates the second signal. This third signal (209) may be triggered by numerous events including: generation of a read signal, generation of a chip select signal, or indication that the end of the data to be written to the memory device (127) has occurred. |
