| 摘要 |
<p>PURPOSE:To put a bus in effective operation by providing a means for varying the number of stages of a buffer for transmission which varies the number of stages of the buffer for transmission, and decreasing the number of stages of the buffer for transmission and restricting the transmission if ineffective transfer on the bus increases. CONSTITUTION:Respective processors 100-103 are connected by an inter-processor bus 108. The processors 100-103 have bus interface devices 104-107 before the inter-processor bus 108. Each of the processor has a bus sequence means 206 which makes transfer from the processor through the bus ineffective if the bus interface device is not ready for reception, a counting means 210 which counts the ineffective transfer of its processor caused in a unit time, and the transmitting buffer stage quantity varying means 211 which varies the number of states of the transmitting buffer 202 in inverse proportion to the counted value; if the ineffective transfer on the bus increases, the number of stages of the transmitting buffer is decreased to restrict the transmission.</p> |
