Multiple processor computer system.

摘要

A multiple processor system is configured to include at least two system or memory buses (110, 112) with at least two processors (102, 104; 106, 108) coupled to each of the system buses (110, 112), and at least one I/O bus (114) which provides multiple expansion slots hosting up to a corresponding number of I/O bus agents (MIU1, MIU2) for the system. Each of the system (110, 112) and I/O (114) buses is independently arbitrated to define decoupled bus systems for the multiple processor system. Main memory for the systems is made up of at least two memory interleaves (118, 120), each of which can be simultaneously accessed through the system buses. Each I/O bus (114) is interfaced to the system buses (110, 112) by an I/O interface circuit (134) which buffers data written to and wread from the memory interleaves (118, 120) by I/O bus agents (MIU1, MIU2). <IMAGE> <IMAGE>