Micro MIS type FET and manufacturing process therefor

摘要

A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 mu m, a second conductivity type channel layer having an impurity concentration of less than 1x1016/cm3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1x1017/cm3 beneath the channel layer.