发明名称 SEMICONDUCTOR INTEGRATING APPARATUS
摘要 PURPOSE:To curtail the area of a test circuit and the number of terminals of test signals by a method wherein a test code train is prepared according to a test signal from outside and rearranged to a serial train to be applied to other integrated circuit areas so that the train is rearranged selectively to a parallel train according to a specified control signal. CONSTITUTION:When a test signal TiN is applied, a test code train TOTp corresponding to a part for TOT of the signal TiN is pick up from a code train generation circuit 30a to be converted to a serial signal TOTs with a parallel/serial conversion circuit 30b. At the same time, a part for CRT of a signal TIN is decoded with a decoder to make one of control signals CTR 1-CTR3 active. When the signal CRT1 is active, the operation of a test circuit in an area 50 is allowed and hence the signal TOTs, is taken into the circuit to be converted into a signal TOTp, which is supplied into the area 50. In this case, a test facilitating structure of a scan type is realized inside the area 50 corresponding to the TOT part of the signal TiN.
申请公布号 JPH0572294(A) 申请公布日期 1993.03.23
申请号 JP19910236149 申请日期 1991.09.17
申请人 FUJITSU LTD 发明人 YAMAMURA TAKESHI
分类号 G01R31/28;G06F11/22;H01L21/82 主分类号 G01R31/28
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