发明名称 INSPECTION SERIES GENERATION DEVICE
摘要 PURPOSE:To generate an input pattern series for detecting a failed portion in a logic circuit. CONSTITUTION:A simulation of a logic circuit 1 for detecting a failure is performed by using a circuit simulator 4. A logic value for an input pattern which is generated by an input signal generation portion 6 is obtained by using the logic simulator 4. The number of procedures for controlling a failed portion is obtained by a controllable cost deriving portion 7 and a continuous logic value of the failed portion is obtained by a continuous logic value deriving portion 8 and then a cost is obtained from these values by a cost deriving portion 9. Costs in each input pattern are compared by a minimum cost deriving portion 10, the minimum cost is obtained, and then an input pattern is selected by an input signal setting portion 11.
申请公布号 JPH0560839(A) 申请公布日期 1993.03.12
申请号 JP19910219891 申请日期 1991.08.30
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NIWA TOSHIO;KAYASHIMA KAZUHIRO
分类号 G01R31/3183;G01R31/28;G06F11/22;G06F11/25;G06F11/26;G06F17/50 主分类号 G01R31/3183
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