发明名称 PSEUDO FAULT TESTING SYSTEM
摘要 PURPOSE:To reduce man-hour for certification by providing a pseudo fault test system which can set the address of a micro-program (muP) in an information processor at the desired timing of generating a pseudo fault without being affected by the change of the muP. CONSTITUTION:A pseudo fault trigger address table 23 registering a trigger muP address group is provided in the muP 22 of a processor 2 for pseudo fault generation, and a pseudo fault trigger parameter table 12 registering a parameter group fro calculating a trigger muP address corresponding to the test timing from the table is provided in a processor 2 for pseudo fault certification. A pseudo fault injection program 11 calculates the trigger muP address from the trigger address table 23 by using the parameter for test in the parameter table 12 and injects the fault by using this address.
申请公布号 JPH0561712(A) 申请公布日期 1993.03.12
申请号 JP19910225653 申请日期 1991.09.05
申请人 HITACHI LTD;HITACHI COMPUT ENG CORP LTD 发明人 SUZUKI MAKOTO;CHIBA NOBUTAKA;ISODA HIDEO
分类号 G06F11/22 主分类号 G06F11/22
代理机构 代理人
主权项
地址