INTEGRATED CIRCUIT HAVING LATCH-UP PROTECTION CIRCUIT FABRICATED BY COMPLEMENTARY MOS TECHNOLOGY,申请号EP19870111569-传众专利搜索

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发明名称	INTEGRATED CIRCUIT HAVING LATCH-UP PROTECTION CIRCUIT FABRICATED BY COMPLEMENTARY MOS TECHNOLOGY
摘要
申请公布号	EP0261370(B1)	申请公布日期	1993.03.10
申请号	EP19870111569	申请日期	1987.08.10
申请人	SIEMENS AKTIENGESELLSCHAFT	发明人	WINNERL, JOSEF, DR.;RECZEK, WERNER
分类号	G05F3/20;H01L27/08;G11C11/407;H01L21/822;H01L21/8238;H01L21/8242;H01L27/04;H01L27/092;H01L27/108	主分类号	G05F3/20
代理机构		代理人
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地址

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