| 摘要 |
PURPOSE:To devise the generating circuit so that a pulse is generated without being affected by a capacitive load, a temperature and an operating voltage by switching a latch circuit into non pulse output state with a delayed signal thereby outputting a pulse till a body to be driven keeps operation after the latch circuit outputting a pulse activates the body to be driven. CONSTITUTION:Since an input signal 8 given to one input of a NAND gate 14 is at a high level and an input signal 10 to the other input of the gate 14 is latched at a high level when the input signal 8 changes to a high level, an output signal 11 of the NAND gate 14 is switched to a low level. The signal 11 is delayed via inverters 15-18 acting like delay circuits and a resulting signal 9 goes to a low level and is inputted to a NAND gate 12. A signal 19 of a NAND gate 13 goes to a high level. Since the input signal 19 to one input of the NAND gate 13 and the input signal 8 to the other input of the gate 13 are at a high level, an output signal 10 of the gate 13 goes to a low level. Thus, the pulse continues to be outputted till a body to be driven is activated. |
