Power reducing buffer/latch circuit

摘要

A data latch/buffer cell for driving a data bus line conditionally precharges the line only during cycles prior those in which data is actually sampled. An input gate selectively enables a data input signal for application to a latching circuit. Prior to application of the data input, a conditional precharge signal is applied to the latch circuit to clear the previously latched data. A latch circuit is coupled to the gate of a pull-down transistor which drives the data bus. The conditional precharge signal is also coupled to the gate of a complementary pull-up transistor to precharge the bus line. Application of the conditional precharge signal to the gate of the pull-up transistor is delayed relative to turning off the pull-down transistor to preclude a rush through current in the driver.