| 摘要 |
PURPOSE:To reduce effectively the transient during the switching of the inverter output, by securing nearly a constant lever for the output of the 1st integrator which forms the PLL. CONSTITUTION:The phase comparator 3 turns the input Pi into the reference clock signal P1 via the divider 1 for the input of one side. And the output P8 of the hysteresis generator 8 is defined as the input of the other side in correspondence to the rectangular wave output P01. Thus a comparison is given to these relative phases. The plus and the minus are delivered in case the output P8 is slower and faster than the signal P1 each. The output P3 of the comparator is integrated and stored by the integrator 4. The multiplier 5 to which the output P2 of the FV converter 2 is applied performs a multiplication between the integral output P4 and the signal P1 to produce the output P5. And the polarity of the output P5 is given inversion and noninversion by the inverter 6 and in accordance with the output P8, and then the output P6 is supplied to the integrator 7 to produce the rectangular wave having a certain inclination. The generator 8 trims the peak value of the rectangular wave. Here the voltage level of the output P4 is set irrespective of the frequency, and thus the output triangle becomes constant and steady regardless of a sudden change of the frequency. |
