| 摘要 |
<p>PURPOSE:To realize the phase adjusting circuit whose scale is smaller than a conventional one and which can adjust quickly a clock phase, with regard to the clock phase adjusting circuit for fetching reception data while shifting to a reference clock of a receiving equipment side from a clock of the receiving data. CONSTITUTION:This circuit is constituted so that a receiving clock and data are written in a data transfer means 1 by a third clock having a high repeat frequency of N folds of a reference clock, a phase difference between the receiving clock and a reference clock is detected by a count value of a third clock, and by varying a read-out timing (read reset) 12 of the receiving clock and the data from the data transfer means 1 by the detected phase difference, a phase difference of the reference clock and the receiving data is adjusted to a prescribed state.</p> |
