Semiconductor device protection circuit.

摘要

FET protection circuit (10; 100) senses the temperature of a FET (11) and, via a control circuit (24), increases FET conduction in response to sensed FET temperature exceeding a high temperature threshold (160C) close to the maximum rated junction temperature (175C) of the FET. This allows the FET to survive excessive drain-to-source voltages which occur during load dump conditions even when load dump is sensed by a zener diode (26) which initially turns on the FET. During load dump after a zener diode (26) turns on the FET, in response to sensing excessive FET temperature the FET is turned on harder so as to reduce the drain-to-source voltage (VDS) and minimize power dissipation during load dump thereby protecting the FET. Normal overcurrent and maximum temperature turn off circuitry (44, 33, 60-63) is effectively overridden by high temperature threshold turn-on circuitry (50). Preferably, a majority of the control circuit (24) is provided on an integrated circuit, but an external resistor (31) allows effective adjustment of two temperature thresholds (150C, 160C) above which control signals provided to the FET will be modified.