发明名称 DETECTING SYSTEM FOR JUNCTOR FAULT
摘要 PURPOSE:To secure the detection with discrimination for the multiplex fault patterns and thus secure a quick and accurate countermeasure to the fault, fractionating the parity check section and furthermore blocking the transmission of the error information to the subsequent positions. CONSTITUTION:Both the parity checker PC1 and the parity generator PG1 are installed at the output side of the time-divisionswitch 200. And in the case of the fault (a), the parity checker PC on the incoming side corresponding junctor highway of the space switch module 20 detects the parity error. In addition, the parity checker PC at the outgoing side also detects the error. Thus the fault can be processed en bloc under the control of the checkers PC since the fault process is carried out through the control circuit 201. In the case of the fault (b), the error is checked through the checker PC1 not by the checker PC for easy distinction. In the case of the fault (c), just one unit of the outgoing side checker PC1 carries out the error detection. And in the case of the fault (d), the error is checked only by the incoming side checker PC of the switch 104. In such way, the fault report is given to the central process module 30 through one unit of the control circuit for one unit of the fault.
申请公布号 JPS5657385(A) 申请公布日期 1981.05.19
申请号 JP19790132926 申请日期 1979.10.17
申请人 OKI ELECTRIC IND CO LTD;NIPPON TELEGRAPH & TELEPHONE;NIPPON ELECTRIC CO;HITACHI LTD;FUJITSU LTD 发明人 MIYOSHI TATSUROU;HIRAI ATSUSHI;KAWADA AKIRA;TOKUNAGA KAORU;KATSUYAMA TSUNEO
分类号 H04M3/26;H04Q1/20;H04Q11/04 主分类号 H04M3/26
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