发明名称
摘要 <p>PURPOSE:To execute initialization corresponding to a program to be executed without interposing assistance, by connecting a low-order bit to the address bus of a CPU, and a high-order bit to the output terminal of a register, out of the address input terminals of a ROM in which plural kinds of programs for the initialization are stored. CONSTITUTION:Out of the address input terminals A0-A14 of the ROM10, the low-order 13 bits A0-A12 are connected to the address bus 3, and the high- order 2 bits A13 and A14 are connected to the outputs QA and QB of the register 11, and the clear terminals CR of flip-flops 12 and 13 consisting of the register 11 are connected to the output of a power-on reset circuit 9. The ROM10 stores the programs INP1-INP4 in blocks 1-4, and those blocks are assigned to the same space on the address space of the CPU1. Also, the initialization programs corresponding to the first and the second modes of the CPU1 are stored as the programs INP1 and INP2.</p>
申请公布号 JPH056208(B2) 申请公布日期 1993.01.26
申请号 JP19860252195 申请日期 1986.10.23
申请人 SANYO ELECTRIC CO 发明人 TSUKAGOSHI MASAMI;MAEHARA HIDEYUKI;OOSHIMA DAISAKU
分类号 G06F1/24;G06F1/00 主分类号 G06F1/24
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