| 摘要 |
Minimal delay rate-change circuits for transmitting data samples partitioned into blocks comprise an arrangement of storage devices (101 through 105) between input (100) and output (600) with individual storage lengths increasing according to a geometric progression; storage means (106) arranged between input and output to store all but one of the remaining samples unallocated to the storage devices; input clocking means (201 through 207) to route input samples to appropriate storage devices or means; and output clocking means (501 through 507) to gate the accumulated samples to the output. The topological arrangement relies on the ability of a storage device to shift out while the next lower size storage device is being loaded. |
