| 摘要 |
<p>An asynchronous computer bus (120) providing transfers of data on consecutive processor clock cycles. The bus comprising consecutive data transfer commence indication means (620, 630), starting address transmission means (401, 501), consecutive data transfer indication means (506, 606), and data transmission means (120). The invention provides for the ''burst'' capabilities of modern processors wherein entire blocks of data are transmitted within a single request.</p> |
