| 摘要 |
<p>Information codes are stored in memory in the form of a data matrix having row addresses and column addresses. The information codes are extracted obliquely to produce a first error-correcting code word and transversely to produce a second error-correcting code word. The first error-correcting code word is produced by extracting the information codes in units of n row addresses (n is 2 or a larger integer). Another memory has addresses corresponding to row addresses of information codes and stores coefficients for use in generating the first error-correcting code word. An accumulator for generating the first error-correcting code word is provided with a two-port memory having writing addresses or addresses corresponding to the row addresses of information codes to be written and reading addresses or addresses corresponding to the row addresses of immediately preceding information codes that are members of the same error-correcting code word as the information codes to be written. Then, the first and second error-correcting code words are generated in parallel. Thus, high-speed processing and simple circuitry are realized. <IMAGE></p> |
