| 摘要 |
<p>A microprocessor including a processing unit, a plurality of external connector terminals, a boundary scan means including a boundary scan shift register having a respective shift register cell associated with each of the plurality of connector terminals, a self test means, logic means including a self test register and said boundary scan shift register, the arrangement being such that the logic means selectively writes data into the registers in order to initiate and to sequence the operation of a self test mode of operation or a boundary scan mode of operation, and wherein the processing unit of the microprocessor is coupled to the self test register for execution of a self test routine. <IMAGE></p> |
