| 摘要 |
<p>A field effect transistor (FET) has a gate electrode (15), a source electrode (14) and a drain electrode (14) formed on a GaInAs/GaAs quantum well layer comprising a stack of an undoped GaAs layer (2), an impurity doped GaInAs layer (3) and an undoped GaAs cap layer (4), has low resistivity regions (11) formed by ion-implantation in a source region and a drain region of the GaInAs/GaAs quantum well layer, has the impurity doped GaInAs layer (3) as a channel, and has a thickness of the undoped GaAs cap layer (4) of 30 - 50 nm. An annealing temperature for activating the low resistivity regions (11) is no higher than a temperature at which the GaInAs/GaAs quantum well is not substantially broken and no lower than a temperature at which a sheet resistivity of the low resistivity regions (11) is sufficiently reduced. The FET thus manufactured has desired functions of the GaInAs/GaAs quantum well and the low resistivity regions (11) and attains a low noise and high speed operation. <IMAGE></p> |
