发明名称 HALBLEITERSPEICHERGERAET.
摘要 Address signals are decoded by partial decoders, to generate in-phase and complementary signals. These signals are selectively input to main decoders consisting of NAND circuits. Further, these signals are fed via through programming fuse elements to a NOR gate. The fuse elements and the NOR gate form a programmable spare decoder. When the bit selected by the main decoder is defective, the output of this main decoder is shut off. Further, the fuse element of the spare decoder is opened corresponding to the main decoder to select the defective bit, thereby to replace the defective bit with the spare bit.
申请公布号 DE3687205(D1) 申请公布日期 1993.01.14
申请号 DE19863687205 申请日期 1986.09.18
申请人 KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP 发明人 FUJII, SYUSO C/O PATENT DIVISION;SAITO, SHOZO C/O PATENT DIVISION, MINATO-KU TOKYO 105, JP
分类号 G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G06F11/20 主分类号 G11C11/401
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