| 摘要 |
PURPOSE:To simultaneously process both data and to cancel the limit of signal processing time by classifying input output data into right channel data and left channel data, latching them respectively, switching them with a control signal and outputting. CONSTITUTION:Data D1 inputted to an input output circuit 10a are serial- parallel-converted by a control signal BCLK at a converting circuit 11, and by a rise edge signal RE of a detecting circuit 14a, Lch data are latched to a latch circuit 12b. Next, by a fall edge signal FE of a detecting circuit 14b, the data of the circuit 12b are latched to a latch circuit 12c, and in the same way, the parallel-converted Rch input data are latched to a latch circuit 12a. Concerning the output, the Lch data are latched to a latch circuit 13b and the Rch data are latched to a latch circuit 13a. By a multiplexer 15, selection is performed by a control signal LRCK, loading is performed to the converting circuit 11 by an edge signal E of a detecting circuit 14, and output is performed as data DO after the parallel-serial-conversion. |
