Digital synthesiser for communications transmitter and receiver and for generator in measurement engineering - has complementary XOR coupled behind D-latch, controlled by system clock pulse

摘要

The circuit uses the principle of phase accumulation and consists of an input circuit (SPA), an adder (ADD), a summation memory (SPS) with feedback to the adder, and complementing EXOR coupled behind the summation memory. Behind the complmenting EXOR is coupled a D-latch (1), controlled by the system clock pulse. The D-latch energises a SIN-ROM (5), behind which are linked further D-latches (2), contrtolled by the system clock pulse, whose outputs switch an R-2R-network (3). Behind the latter is preferably coupled a FET (4). The SIN-ROM may have a greater number of inputs than outputs. ADVANTAGE - High spectral cleanliness and high clock pulse frequency at low power requirements.