发明名称 Frequency divider with reduced clock skew
摘要 A first frequency dividing circuit receives an input clock signal from an input terminal and divides the frequency of the input clock signal to produce a first signal which it supplies to an output terminal. A second frequency dividing circuit divides the frequency of the input clock signal to produce a second signal having the same frequency as the first signal but differing from the first signal in phase. The second signal controls a gating circuit. When switched on, the gating circuit connects the output terminal to the input terminal, or to an auxiliary power-supply or ground terminal, thereby deskewing the signal at the output terminal.
申请公布号 US5175752(A) 申请公布日期 1992.12.29
申请号 US19910772939 申请日期 1991.10.08
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 YOKOMIZO, KOICHI
分类号 H03K23/00;H03K23/50 主分类号 H03K23/00
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