Method of designing semiconductor integrated circuit device

摘要

A method for designing a semiconductor integrated circuit device using a standard cell or gate array method. A chip is divided into a plurality of blocks to realize a hierarchical layout design in units of blocks. A first scheme is preferentially dividing a first module constituting a logical connection description and having a large height and an occupation area smaller than standard value. A second embodiment is preferentially dividing a second module having a small height and an occupation area larger than a standard value. The first and second embodiments are selected in accordance with a hierarchical structure of the modules in a logical connection description. Thereafter, processing for dividing the first or second module in correspondence with areas of the plurality of blocks is executed using a computer on the basis of the selected one of the first and second embodiments.