CIRCUIT FOR CONTROLLING PATH OF ADDRESS OF CACHE MEMORY

摘要

The circuit controls address path in a copyback and writeback mode effectively. The circuit includes a comparator (11) for generating retry signal by comparing input and output address signals with each other, a CPU cache address path former (12) for generating cache state memory (6b) address and cache tag memory (6a) address according to address signal transmitted from a CPU, a snoop cache address path former (13) for generating snoop state memory (6d) address and snoop tag memory (6c) address, a data cache address path former (14) for transmitting address signals to a data memory, and a system address bus generator (15) for transmitting address signals to a system bus controller (2) according to address signals transmitted from the cache address path former (12) and the snoop cache address former (13).