MOS transistor with reduced short channel effect and series resistance - uses three implant levels for drain-source which are self-aligned using a double layer spacer

摘要

The metal-oxide semiconductor (MOS) transistor is made using the following process steps: after formation of the gate dielectric layer, gate-electrode and gate insulator structure an insulating layer (5), pref. Si-nitride, is deposited followed by a semiconductor layer (6), pref. undoped polysilicon, or another insulation layer with a different etch rate, pref. Si-dioxide. This double layer is etched to leave double layer spacers (5a,6a) at the edges of the gate electrode. The etching action is pref. anisotropic, pref. carried out using dry etching, especially using RIE. A first implantation (8) of drain/source dopant is carried out. Then the semiconducting spacer (6a) is removed and a second, pref. lower level, implantation (9) of drain/source dopant carried out. The insulating part of the spacer (5a) is then removed and a third, pref. lowest level, implantation (10) carried out of the drain/source dopant. Also claimed is a first insulation layer (5) which is sufficiently thin to allow diffusion of dopant through it to take place. The gate dielectric and gate insulator layer are pref., SiO2 layers, the gate electrode is pref. doped poly Si. USE/ADVANTAGE - The structure has the advantage of a lower resistance lightly-doped-drain (LDD) structure, which has a lower sideways diffusion, resulting in a longer channel than conventional devices. This is manifested in a higher Vt than conventional devices and a lower leakage current. The substrate current is lower also, e.g. by a factor of about 5, than conventional devices, which shows a reduced carrier generation rate, and so a reduced injection rate into the dielectric. The stability of the Vt is consequently better. The structure is used in the mfr. of 64Mbit DRAMs.