| 摘要 |
<p>PURPOSE:To provide an access method to plural memories which can minimize an address bus and a control signal line. CONSTITUTION:An address bus 31 to one frame memory and a control signal line 32 for access are commonly used for the (m) number of frame memories 1-m and the address of the frame memory is divided into the (m) number. For the data for writing, a parallel converting means 10 converts the (m) number of the data to a parallel signal, sends the (m) number of the frame memories 1-m, and to the address position of the address area assigned from an address bus 31, writes (n) bit each in accordance with the writing signal from the control signal line 32. At the time of reading, from the address position of the address area assigned from the address bus 31 of the (m) number of the frame memories 1-m, (n) bit each is read in accordance with the reading signal from the control signal line 32, inputted to a serial converting means 20, converted to a serial signal for each (n) bit and outputted successively.</p> |
