| 摘要 |
A twenty four bit digital-to-analog converter comprising three eight bit digital-to-analog converters. The outputs of the two least significant converters are proportioned and summed together into one amplifier to form a sixteen bit converter. The most significant converter is fed to a separate amplifier. The output of the two amplifiers is summed into a square-root amplifier through various analog switches and summing resistors. Gains at the input and output of the square-root amplifier are altered according to the input level of the digital-to-analog converter in order to optimize the dynamic range and gain requirements. |
