| 摘要 |
PURPOSE:To quicken a frequency lock time and to obtain a transmission signal with less residual FM and a high S/N. CONSTITUTION:PLL frequency synthesizers 6,7 use lock detection circuits 9, 11 to detect the frequency lock. Then time constant changeover circuits 8, 10 are used to switch a loop filter time constant so that the response is quickened before the frequency lock after the frequency of the PLL frequency synthesizers 6,7 is made stable and the response slows down after the frequency lock. In this case, when the time constant in time constant changeover circuits 8,10 is the output of the circuits 8,10 is delayed by delay circuits 12,13 respectively thereby reducing the fluctuation in the PLL loop. |
