| 摘要 |
PURPOSE:To attain serial/parallel conversion and parallel/serial conversion in the unit of optional bits by storing an input data in the unit of optional bits and writing/reading the data in a set clock timing. CONSTITUTION:An input data DIN is fetched sequentially to a shift register 5 via a buffer 4 in the unit of N bits in the timing signal from an input decoder 1 driven by an input clock. Then an input enable signal is fed to the input decoder 1 and the storage data in the register 5 is fetched in a latch 6 in the unit of N bits and written one by one bit each to N sets of memory planes of a memory cell array 7. The read is controlled by a parallel output clock fed to an output decoder 2 and a parallel output enable signal from a control circuit 3 and N bits data are once read from the memory cell array 7 and outputted to an output buffer 8. Thus, the data is processed in the unit of optional parallel bits and the processing speed is improved and the peripheral circuit is simplified. |
