| 摘要 |
<p>PURPOSE:To enable a semiconductor integrated circuit device in a multilayer interconnection structure to be enhanced in electrical reliability, degree of integration, and operational speed and another semiconductor integrated circuit device in a multilayer connection structure where a memory aggregate and a logic section are constituted through a Bi-CMOS technique to be enhanced in electrical reliability, degree of integration, and operational speed. CONSTITUTION:In a semiconductor integrated circuit device 2 provided with a multilayer interconnection structure, a first wiring 32 formed of conductive material higher than that of a second wiring 36 provided to an upper wiring layer in allowable current density per unit area is provided to a lower wiring layer, and the product of the cross-sectional area in a wiring widthwise direction and the allowable current density of the first wiring 32 is set nearly equal to that of the second wiring 36.</p> |
