发明名称 MULTIPLIER
摘要 PURPOSE:To attain the high speed of an arithmetic operation by dividing a full adder with a carry look ahead into the high-order side of the number of the power of 2, and the low-order side of the edge number, and completing the arithmetic operation of the low-order side until the arithmetic operation of the high-order side is started. CONSTITUTION:A number to be operated is used as the complement of 2, and a multiplication is operated by using the algorithm of a booth. A full adder CLA with a carry look ahead is used as the adder which communicates the carry at a final stage to a digit direction, and it is divided into a high-order side CLA1 and a low-order CLA2. Then, the high-order side is defined as the number of digits corresponding to the number of the power of 2, the low-order side is defined as the number of digits corresponding to the number of digits of the edge number overflowing from this, and the carry of the low-order side CLA2 is inputted to the high-order side CLA1. An input to the low-order side CLA2 is early decided, and then the arithmetic operation of the low-order side CLA2 is completed at the time of starting the arithmetic operation of the high-order side CLA1, and the carry of this result is inputted to the high-order side CLA1. Thus, the entire arithmetic operation can be decided only by the operation time of the high-order side CLA1 regardless of the operation time at the low-order side, so that the operation time can be shortened.
申请公布号 JPH04354020(A) 申请公布日期 1992.12.08
申请号 JP19910129703 申请日期 1991.05.31
申请人 SANYO ELECTRIC CO LTD 发明人 IIJIMA HIROAKI
分类号 G06F7/533;G06F7/508;G06F7/52;G06F7/53 主分类号 G06F7/533
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