Vector bit-matrix multiply functional unit

摘要

A method and apparatus provides bit manipulation of data in vector registers of a vector register computer system. Matrix multiplication is accomplished at a bit level of data stored as two matrices in a vector computer system to produce a matrix result. The matrices may be at least as large as 64 bits by 64 bits and multiplied by another 64 by 64 matrix by means of a vector matrix multiplication functional unit operating on the matrices within a vector processor. The resulting data is also stored at a 64 bit by 64 bit matrix residing in a resultant vector register.