JITTER DECREASING DEVICE

摘要

The apparatus reduces jitter generted during byte stuffing process in reverse mapping process tributery unit/administrate unit signal to virtual container level n signal. The apparatus includes an elastic buffer (1) for receiving tributary/administrate unit data, address generators (2,3) for generating writing and reading address by writing clock signal and the most significant bit of virtual container level respectively, a bit leaking processor (4) for calculating stuffing generation interval according to frame clock and positive/negative stuffing data, a divider (15) for dividing frequency of adjusted clock by 12, a phase smoothing circuit (6) for generating VCn clock signal and a frequency divider (7) for dividing VCn clock signal by 8.