| 摘要 |
<p>PURPOSE:To provide the cycle of a frame counter from being shifted even when the same pattern as a synchronizing code exists in data while the frame counter reset by the detecting pulse of the synchronizing code is under counting in the cycle of one frame. CONSTITUTION:When a pattern comparator 2 detects the synchronizing code and the detecting pulse is outputted and inputted to a gate circuit 4, the detecting pulse is passed by the gate circuit 4 and inputted to a frame counter 5 and the frame counter 5 is reset. When the frame counter 5 is reset, a gate signal generator 3 impresses a gate signal to the gate circuit 4 so as to inhibit that the detecting pulse is outputted from the gate circuit 4 even when it is inputted from the pattern comparator 2 to the gate circuit 4. Thus, the frame counter 5 is not reset again by a pseudo synchronizing code existent in one frame after it is reset.</p> |
