发明名称 SCAN PASS LOGIC VERIFYING SYSTEM
摘要 PURPOSE:To surely execute the verification of scan pass logical connection in a CAD. CONSTITUTION:A model information storing means 1 stores a simulation model, scan pass wiring order indicating the order of flip flops(FFs) and scan pass control signal information defining a control signal for driving a scan pass. A simulation control instruction output means 2 applies codes inherent in respective FFs to respective FFs as respective initial status values based upon the stored information and forms an instruction for executing code propagation simulation for propagating respective codes on the scan pass. A code propagation simulation executing means 3 executes code propagation simulation in accordance with the instruction. An expected value comparing means 5 compares an expected value formed by an expected value generating means 4 with a simulation result obtained from the means 3 to discriminate whether the logical connection of the scan pass is invalid or not.
申请公布号 JPH04340173(A) 申请公布日期 1992.11.26
申请号 JP19910140831 申请日期 1991.05.16
申请人 NEC CORP 发明人 FUJII TOSHIAKI
分类号 G06F11/22;G06F11/25;G06F11/26;G06F17/50 主分类号 G06F11/22
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