发明名称 |
A complementary low power non-volatile reconfigurable eecell. |
摘要 |
<p>A non-volatile CMOS electrically erasable programmable memory cell for configuring a PLD is disclosed. A CMOS inverter is formed by fabricating an n-channel MOSFET and a p-channel MOSFET with merged floating gate regions. A tunnel capacitor allows charge to be supplied to or removed from the floating gate. The floating gate provides non-volatile charge storage. The CMOS inverter senses the presence or absence of charge on the floating gate and provides an amplified inverted output. The CMOS inverter consumes very low power and provides rail-to-rail output voltage swings. <IMAGE></p> |
申请公布号 |
EP0515039(A2) |
申请公布日期 |
1992.11.25 |
申请号 |
EP19920303626 |
申请日期 |
1992.04.23 |
申请人 |
ALTERA CORPORATION |
发明人 |
TURNER, JOHN E.;CLIFF, RICHARD G. |
分类号 |
G11C17/00;G11C16/04;H01L21/82;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;H03K19/173 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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