| 摘要 |
<p>A pulse discriminating circuit discriminates narrow input pulses from an input pulse signal (IN11) for eliminating output pulses corresponding to the narrow pulses from an output pulse signal (OUT11) thereof, and comprises a delay unit (11) supplied with the input pulse signal for introducing predetermined time delay into propagation of the input pulse signal in synchronism with a two-phase clock signal (CLK1/ CLK2), and an eliminating unit (13) responsive to output signals of the delay unit and operative to produce the output pulse signal consisting of output pulses corresponding to wide input pulses, wherein the delay unit comprises early stages (FF11/ FF12) responsive to the two-phase clock signal for transferring the input pulse signal, and later stages (FF13/ FF14/ FF15) responsive to a transfer signal (CLK3) lower in frequency than the two-phase clock signal for transferring the input pulse signal so that the predetermined time delay is prolonged without increasing the number of stages of the delay unit. <IMAGE></p> |
