| 摘要 |
<p>PURPOSE:To decrease competition delay and to accelerate memory access by dividing the individual memory of each processor into a peculiar data area and a shared data area. CONSTITUTION:When a test and set request signal 300 is transmitted and a competition circuit 30 selects competition to a request from the other processor, a test and set permitting signal 301 is returned and simultaneously, a signal 302 under test and set is transmitted to the individual memory of the other processor. Then, the test and set of the shared data area due to the other processor is inhibited and only the test and set due to the selected processor is processed. After a flag is completely set, the request signal 300 is canceled, and the test and set is enabled for the other processor. When the flag is temporarily set, the other processor disbales the set of the own processor number due to the test and set until the flag is set, and shared resource access is inhibited.</p> |
