| 摘要 |
<p>PURPOSE:To suppress increase of a process and to enhance reliability even when the circuit is interfaced with a device inputting and outputting a signal at a power supply voltage level higher than a power supply voltage of the circuit itself. CONSTITUTION:The input output buffer circuit is provided with an input output terminal PAD inputting and outputting a signal at the outside of the circuit, an input buffer circuit 2 receiving a signal from the input output terminal PAD, an inverter circuit 3 driven by a 1st power supply VCC1, a P-channel MOS transistor(TR) QP3 whose one terminal connects to the 1st power supply VCC1, whose other terminal connects to the input output terminal PAD and whose base connects to a 2nd power supply VCC2, an N-channel MOS TR QN4 connected to a round potential terminal, and an N-channel MOS TR QN2 connecting to the output terminal N3 of the inverter 3 or the like, and even when a signal of the same potential as that of the 2nd power supply VCC2 is inputted from the input output terminal PAD, no forward bias is caused and input leakage current and a through-current are prevented.</p> |
