| 摘要 |
PURPOSE:To reduce a reception error, by automatically correcting the phase relation between the data and the clock through the use of a phase locked loop. CONSTITUTION:A clock synchronizing signal pickup circuit 4 picks up the synchronizing signal from the character data (a) to introduce the signal (c). An automatic variable phase shifter 7 controls the phase with an amplifier 12 constituting a PLL circuit. If the phase between the data (a) and the signal (g) is shifted, the phase comparator 8 produces a detection voltage. This voltage adjusts the phase of the signal (g) via a LPF10 and the amplifier 12. Thus, since the phase of clock is locked to the clock synchronizing signal of the character information through the use of a PLL circuit, the write-in error to a buffer memory 2 due to phase shift is reduced, allowing to prevent the mis-reception. |
