| 摘要 |
PURPOSE:To reduce switching noise of an image sensor extracting a picture signal in time series and to improve the S/N of an image sensor output by devising the shift register such that only the switching noise by a clock required for pulse shift is generated in each D flip-flop. CONSTITUTION:Plural D flip-flops are connected in series. A logic circuit outputting only a clock required to shift a data input pulse from a data input terminal of a D flip-flop to its output terminal is added to an input terminal of each D flip-flop. That is, a clock input terminal CK connects to one input of a NOR circuit 3 of an addition circuit 10 comprising the series connection of a NAND circuit 1, an inverter 2 and a NOR circuit 3 and an output of the NOR circuit 3 and an output of the NOR circuit 3 via an inverter 8 are connected respectively to a terminal CK and a terminal inverse of CK of clocked inverters 12, 14, 15, 17. |
