| 摘要 |
<p>PURPOSE:To prevent a generation of mishit caused by the block size difference between a first order cache and a second order cache by varying the amount of data, which are simultaneously transferred between a first and a second memory arrays located on the same single chip, via an external signal. CONSTITUTION:Each of the block transfer gates 15 and 17 of DRAM memory array 13 and SRAM memory array 18 located on the same single chip are controlled by each of the external signals from a data transfer amount control circuit 5. By this scheme, the amount of data simultaneously transferred between the arrays 15 and 17 becomes variable and the amount of data transferred from the second order cache, which is formed using arrays 13 and 18, to the first order cache as one block worth is set depending on the block size of the first order cache. As a result, the generation of mishit is prevented during the data exchange between the first order cache and the second order cache.</p> |
