| 摘要 |
Disclosed is a circuit for testability which is incorporated in a system LSI comprising a plurality of master modules (1 and 2) and a plurality of slave modules (4 and 5), a common bus (40) for connecting the master modules (1 and 2) and the slave modules (4 and 5), and a bus arbiter (3) for adjusting use of the common bus (40), comprises: tri-state buffers (15 and 16) and control lines for prohibiting transmission of an acknowledgement signal to be transmitted from the bus arbiter (3) to a master module (1) to be tested among the plurality of master modules (1 and 2) in a test mode, which input an acknowledgement signal generated from the master module (1), and which output it to the slave modules (4 and 5); an AND gate (17) for masking acknowledgement signals to be transmitted from the bus arbiter (3) to master modules (2) other than the master module (1) to be tested; a test I/O bus (comprising control lines and data lines) for carrying out Initial setting to a memory portion (22, 26, and 28) in the master module (1) to be tested, and reading data stored in the memory portion (22, 26, and 28); and an ordinary operation control line for setting the master module (1) and the slave modules (4 and 5) into an ordinary operation mode. <IMAGE> |
