| 摘要 |
PURPOSE:To enable a DRAM cell and an E<2>PROM cell to be mounted mixedly effectively and an occupation area of the cell to be nearly equal to that of a normal DRAM cell or E<2>PROM cell. CONSTITUTION:A floating gate(FG) of a transistor (T2) constituting an E<2>PROM cell is extended to a middle portion between a source and a drain. A memory node (NP) is connected to a source of a transistor (T1) constituting a DRAM cell. One portion of this memory node (NP) is provided on the floating gate (FG) through an insulation layer and a low-layer portion (NP1) which is at the same level as that of the floating gate (FG) of this memory node (NP) is positioned at a middle point between the source and drain of (T2). A control gate (CG) as a plate electrode is provided on this memory node (MP) through an insulation layer. |
