| 摘要 |
PURPOSE:To eliminate a need for a dedicated booster circuit and to enable a high speed operation by boosting a word line with the restoration of a bit line itself. CONSTITUTION:Preliminarily at the time of precharging, an EQL signal is set to 'H' and bit lines, BL0, the inverse of BL0, BL1 the inverse of and -BL1 are precharged to a ground voltage Vss, and then a selected word line WL is raised to a power voltage Vcc by a transistor Q0. Since the voltage is not boosted to a boost voltage, the high speed operation can be enabled. After reading cell data out of a memory cell, a signal phi0 is set to an 'H' level and the word line WL is brought into a floating state. Then sense amplifiers SA0 and SA1 are actuated to amplify the difference in the signal between the bit lines BL pair. When the bit lines are restored when the bit line the inverse of BL0 is changed from the Vss to the Vcc and the bit line BL0 is changed from the Vcc to Vss, the word line WL is boosted by the coupling of a transfer gate Q2 of the memory cell. |
