发明名称 FRAME SYNCHRONIZING PROTECTION CIRCUIT
摘要 <p>PURPOSE:To shorten time necessary for acquisition of synchronism at the time of switching channels. CONSTITUTION:In a counter control circuit 103, unmatch bit number CQ1 counted at an unmatch bit counter 102 is compared with first and second threshold values Thp1 and Thp2 for front protection operation. As the result, when the unmatch bit number CQ1 is the first threshold value Thp1 for front protection operation, the normal synchronization recovery is performed by one counting operation of a state counter 104, whereas two or three counting operations of the state counter 104 are performed when the unmatch bit number CQ1 is the second threshold value Thp2 for front protection operation.</p>
申请公布号 JPH04297153(A) 申请公布日期 1992.10.21
申请号 JP19910062068 申请日期 1991.03.26
申请人 TOSHIBA CORP 发明人 OKITA SHIGERU
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
代理机构 代理人
主权项
地址
您可能感兴趣的专利