发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To prevent the self-running of a voltage controlled oscillator by selecting one from plural input reference clocks, oscillating the voltage controlled oscillator synchronously with the clock and selecting other clock when the input reference clock is abnormal. CONSTITUTION:A frequency dividing means 13 receives a 1st reference and one or two more 2nd reference clocks as input signals and outputs a reference clock having a prescribed frequency relation with a 1st reference clock. A selective circuit 14 selects one of output clocks of the frequency dividing means 13 and outputs the selected clock to a phase comparator 11. A fault detection circuit 15 receives the reference clock and controls the selective circuit 14 when the reference clock of the clock selected by the selective circuit 14 has a fault to select and output the other clock. Thus, when an input reference clock synchronously with the voltage controlled oscillator 12 is abnormal, other clock is selected so that the voltage controlled oscillator 12 is not subject to the self-running in an uncontrolled state and oscillates a master clock with stable accuracy at all times.
申请公布号 JPH04291819(A) 申请公布日期 1992.10.15
申请号 JP19910057318 申请日期 1991.03.20
申请人 FUJITSU LTD 发明人 SATO ATSUSHI
分类号 H03L7/08;G06F1/04;H03L7/14 主分类号 H03L7/08
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